MediaTek, a leader in semiconductor design, has announced its advancement in artificial intelligence chips by incorporating sophisticated packaging solutions from both Intel and TSMC. This strategic move marks MediaTek as a key player in a select group of companies navigating the evolving AI hardware supply chain.
MediaTek has effectively integrated Intel's Embedded Multi-die Interconnect Bridge, commonly referred to as EMIB, with TSMC's advanced packaging technologies known as CoWoS and SoIC. This capability allows the company to merge multiple chip dies into a single high-performance package, utilizing two distinct manufacturing ecosystems to enhance productivity and flexibility.
Why did MediaTek choose dual sourcing for its packaging needs? The primary reason is capacity constraints. TSMC's CoWoS packaging has been facing significant supply issues, leading to an increased demand from major hyperscalers and chip manufacturers.
MediaTek proactively sought alternatives. By qualifying Intel's EMIB as a suitable option for 2.5D chip integration, the company is providing its clients—particularly those in cloud and data centers—with a reliable second option when TSMC's production lines are at capacity.
Furthermore, other companies, including Marvell, are also examining Intel EMIB as a viable substitute for TSMC's limited CoWoS offerings. MediaTek's confirmation of support for both packaging ecosystems exemplifies how the semiconductor sector is diversifying amidst the demands of AI technological advancements.
This initiative seems to be driven by a project focused on developing a training-oriented TPU, utilizing TSMC’s N3P process node that aligns with Google’s tensor processing unit development plans. Even when the chip is manufactured by TSMC, it can be packaged elsewhere, which provides flexibility in operations.
Looking at the financial implications, MediaTek recently increased its revenue forecast for data center AI chips from $1 billion to $2 billion by 2026, signaling confidence in the growth of this market segment. On the technical side, Intel's EMIB is scaling up to accommodate larger package sizes—targeting up to 8x reticle by 2026. This allows for greater chiplet accommodation, higher memory capacities, and enhanced computation capabilities. In contrast, TSMC’s current CoWoS packaging technology has certain physical limitations that EMIB aims to surpass.